A semiconductor integrated circuit chip is typically fabricated with a back-end-of-line (BEOL) interconnect structure, which comprises multiple levels of metal lines and inter-level metal vias, to connect various integrated circuit components and devices that are fabricated as part of a front-end-of-line (FEOL) layer of the semiconductor integrated circuit chip. Current state of the art BEOL process technologies typically implement copper to form BEOL interconnects, as the use of copper material is known to significantly reduce resistance in the BEOL interconnect structure, resulting in improved conduction and higher performance.
Conventional metallic interconnect structures utilize copper diffusion barrier layers (e.g., tantalum nitride (TaN)) to line exposed sidewall and bottom surfaces of openings (e.g., trench openings and via openings) that are patterned in an interlevel-dielectric (ILD) prior to filling the openings with copper material. The diffusion barrier layer prevents copper from diffusing into the dielectric material of the ILD layer and damaging the BEOL structure. However, as copper interconnects are scaled down to 7 nm and beyond, the use of diffusion barrier layers becomes problematic. As feature size decreases, the number of challenges in fabrication defect-free copper interconnects increases. For example, physical vapor deposition (PVD) typically provides non-uniform coverage along sidewalls of a trench or via. With trenches getting narrower, the PVD copper seed layer must be make thinner, in order to prevent pinch-off at the top of the trench, and allow enough volume for Copper plating. For certain feature sizes and aspect rations, this can result in incomplete Copper seed coverage.
For example, copper diffusion barrier layers must be made sufficiently thick to adequately prevent diffusion of copper atoms into the ILD layer. The required thickness of the copper diffusion barrier layer remains relatively constant as the line width of copper interconnects scales down. As such, the amount (volume) of the metal line which is composed of copper is reduced which, in turn, affects various line width-dependent characteristics such as grain structure and resistivity.
Moreover, since diffusion barrier layers are typically formed of a material (e.g., TaN) which does not sufficiently act as a wetting layer for electroplated copper, a thin seed layer is typically formed via PVD or chemical vapor deposition (CVD) on the diffusion barrier layer prior to the copper fill. The combined thickness of the diffusion barrier layer and the seed layer can adversely affect the copper filling ability due to a further narrowing of already narrow lines. For Copper interconnects of 7 nm and beyond, it is difficult to secure good enough coverage of barrier metal because of spatial limitations. It is also difficult to avoid the creation of top center voids caused by pinch-off during a copper electroplating process due to a small gap opening. Indeed, when conventional plating techniques are used to fill high aspect ratio vias or trenches, seams and voids develop within the electroplated metallization and these seams and voids inevitably affect contact performance.